Comfort and familiarity. They’re comfortable chips you can learn inside and out with a fairly huge ecosystem (importantly one that is approachable because it’s also powered by people in a similar position and with similar priorities/concerns to your own) around the parts/arch/IS and you don’t have to read scary looking 600-page datasheets (then realize there’s a separate datasheet for the core vs the rest), worry about soldering TQFN or TFBGA packages with your (t)rusty old Weller iron, don’t need to learn the distinction between the Cortex Core and the manufacturer-specific everything else around it, worry about things like initializing timers and peripheral buses, concern yourself too much with power states, etc. If the chip can’t do DMA and can’t do hardware-accelerated x, y, or z, it takes a lot of pressure off of things when it comes to nerd-sniping yourself into doing something in a better way or even just deciding “this isn’t possible, might need to pick a different approach/problem/solution altogether.”