For doing SPI within an FPGA under these rules, you would have the input clock as a signal sampled by the FPGA clock not used as a flop clock, and detect a falling edge synchronously with a chain of two flops.

Works very well so long as master clock speed >> SPI speed.

True, but many slow uCs support system clock == SPI clock. Probably not as relevant these days with 99% of stuff happening on 32-bit devices with clocks so fast you would need RF experience to route SPI at system clock.

For the most part, you shouldn't map SPI peripheral clocks directly to FPGA clocks. They are two very different things. Instead, treat the SPI clock as just another I/O signal.