huh, ofc I only have experience with ring buffers from AMD gpus and USB xHCI controllers, and only heard that NVMe has ring buffers.
It seems USB xHCI is the "most concurrent friendly" and hardwarely friendly (IOMMU and non-IOMMU) as it supports "sparse ring buffers" (non continous in bus address space). AMD gpu ring buffers are atomic read/write pointers (command ring buffers and "interrupt"/completion ring buffers) with doorbells to notify pointer updates.
I should have a look at linux IO uring to see how far they did go and which model they did choose.
I wonder how modern hardware could use anything else than command ring buffers.
Look at AMD gpu command buffers, and xHCI (and NVMe).
But among those "ring buffers", which one is the best? (from a consumer/producer concurrent access, on a modern CPU ofc).
If the commands are not convoluted, the programming is soooo much simpler and cleaner.